alexforencich / verilog-ethernet
Verilog Ethernet components for FPGA implementation
See what the GitHub community is most excited about today.
Verilog Ethernet components for FPGA implementation
FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket
Open source FPGA-based NIC and platform for in-network compute
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Verilog Configurable Cache
PicoRV32 - A Size-Optimized RISC-V CPU
HDL libraries and projects
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/